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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
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Tool: Synplify Pro (R)
Build: W-2024.09LR-SP1-1
Install: C:\lscc\radiant\2025.1\synpbase
OS: Windows 10 or later
Hostname: D-GM0GK9EK

Implementation : impl_1

# Written on Mon Feb  9 10:40:15 2026

##### DESIGN INFO #######################################################

Top View:                "led"
Constraint File(s):      "C:\lscc\radiant\2025.1\scripts\tcl\flow\radiant_synplify_vars.tcl"




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################


Clock Summary
*************

          Start           Requested     Requested     Clock        Clock                                          Clock
Level     Clock           Frequency     Period        Type         Group                                          Load 
-----------------------------------------------------------------------------------------------------------------------
0 -       led|osc_clk     200.0 MHz     5.000         inferred     Inferred_clkgroup_0, Inferred_clkgroup_0_1     28   
=======================================================================================================================


Clock Load Summary
******************

                Clock     Source            Clock Pin          Non-clock Pin     Non-clock Pin
Clock           Load      Pin               Seq Example        Seq Example       Comb Example 
----------------------------------------------------------------------------------------------
led|osc_clk     28        osc_clk(port)     count_num[0].C     -                 -            
==============================================================================================



Clock Relationships
*******************

Starting        Ending          |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-------------------------------------------------------------------------------------------------------------------------------------------
led|osc_clk     led|osc_clk     |     5.000            |     No paths         |     No paths         |     No paths                         
===========================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:LED_0[0]
p:LED_0[1]
p:LED_0[2]
p:LED_0[3]
p:LED_0[4]
p:LED_0[5]
p:LED_0[6]
p:LED_0[7]
p:LED_1[0]
p:LED_1[1]
p:LED_1[2]
p:LED_1[3]
p:LED_1[4]
p:LED_1[5]
p:LED_1[6]
p:LED_1[7]
p:rst


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report